Intel and Micron Tuesday announced that their joint NAND flash manufacturing venture will begin using a more dense circuitry that will allow a terabit of data, or 128 gigabytes, to fit on a fingertip.
The joint venture, IMFT (IM Flash Technologies), said today it has created the world's first 20nm (nanometer), 128Gbit MLC (multilevel-cell) NAND flash die.
The new 20nm chips have the highest capacity for their form factor of any in the market today and are targeted for use in tablets, smartphones, and other consumer electronic devices.
The die doubles the capacity of the venture's 25nm lithography process, which has been used to make the 64Gbit dies used in today's SSDs (solid-state drives), tablets, and smartphones.
The company Tuesday also announced mass production of new 64Gbit dies using 20nm process technology.
Samples of the 128Gbit device will be available in January, closely followed by mass production later in the first half of 2012, IMFT stated.
The new 128Gbit dies will allow manufacturers to double the capacity of SSDs and other NAND-based storage products, enabling a single device to hold 16GB of data and an 8 die chip to hold 128GB of data.
IMFT first announced its 20nm technology in April.
A size comparison between IMFT's current NAND flash chips
Doubling the density of the NAND flash will also "significantly" reduce manufacturing costs associated with wafer production, an IMFT spokesperson said.
IMFT's 128Gbit die uses the Open NAND Flash Interface 3.0 specification, offering performance of up to 333 megatransfers (1 megatransfer = one million data units per second).
"As portable devices get smaller and sleeker, and server demands increase, our customers look to Micron for innovative new storage technologies and system solutions that meet these challenges," Glen Hawk, vice president of Micron's NAND Solutions Group, said in a statement. "Our collaboration with Intel continues to deliver leading NAND technologies and expertise that are critical to building those systems."
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